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King Billion Electronics Co., Ltd.

HE89C21
HE80000 SERIES
- Table of Contents 1. 2. 3. 4. 5. 6. 6.1. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. General Description ___________________________________________________________________1 Features _____________________________________________________________________________2 Pin Description _______________________________________________________________________2 Pad Diagram _________________________________________________________________________4 Pad Coordinations ____________________________________________________________________4 LCD Power Supply ____________________________________________________________________5 LCDC Control register ______________________________________________________________6 LCD RAM Map ______________________________________________________________________6 Oscillators ___________________________________________________________________________7 General Purpose I/O___________________________________________________________________8 Timer1 ____________________________________________________________________________9 Timer2 ___________________________________________________________________________10 Watch Dog Timer __________________________________________________________________12 Low Voltage Reset _________________________________________________________________13 Dual-Tone Multiple Frequency Generator______________________________________________13 Absolute Maximum Rating __________________________________________________________14 Recommended Operating Conditions _________________________________________________15 AC/DC Characteristics _____________________________________________________________15 Application Circuit_________________________________________________________________16 Important Note ____________________________________________________________________16 Updated Record ___________________________________________________________________16
1. General Description
HE89C21 is a member of 8-bit Micro-controller series developed by King Billion Electronics for telecom applications. This chip has 4-COM x 32-SEG LCD driver with built-in regulator to provide stable visual effect over the battery life, 16-bit general purpose I/O port, DTMF generator for the dialing tone generation. It is suitable for application in feature telephone products. The instruction set of HE80000 are easy to learn and simple to use. Thirty-two instructions with four-type January 20, 2003 1 V1.0E
King Billion Electronics Co., Ltd.

HE89C21
HE80000 SERIES
addressing mode are provided. Most of instructions take only 3 oscillator clocks to execute.
2. Features
2.4V ~ 5.5V 16 KB Program ROM 512 Bytes. Fast clock: 32768 ~ 8M Hz Slow clock: 32768 Hz Operation Mode: Fast, Slow, Idle, Sleep Mode. 16 bit Bi-directional general purpose I/O port with output type (push-pull or open drain) selectable for each I/O pin by mask option. 4 COM x 32 SEG LCD driver (A, B type waveform selectable). Built-in Regulator for providing LCD with a stable operation voltage over the battery life. Built-in DTMF Generator. Built-in Low Voltage Reset function Two external interrupts and three internal timer interrupts. Two 16-bit timers and one Time Base timer. Watch Dog Timer to prevent deadlock condition. Instruction set: 32 instructions with 4 addressing modes. Operation Voltage: Internal ROM: Internal RAM: Dual Clock System:
3. Pin Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PRTC6 PRTC7 PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 DTMFO MUTE VDD SXI SXO 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 PRTC5 PRTC4 PRTC3 PRTC2 PRTC1 PRTC0 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 TSTP FXI FXO RSTP GND LV3 LV2 LV1 LC2 LC1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
HE89C21
Pin Name PRTC[7..0] SEG[31..0] COM[3..0] LC1 LC2
Pin #
I/O
66,67,1~6 B 7 ~ 38 39 ~ 42 43 44 O O B B
Description 8-bit bi-directional general purpose I/O port C. The output type of I/O pad can also be selected by mask option MO_CPP[7..0] (`1' for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, `1' must be outputted before reading the pin. LCD SEGMENT SEG[31..0] outputs. LCD COMMON COM[3..0[ outputs. Charge Pump Capacitor Pin Charge Pump Capacitor Pin
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18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3
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Pin Name LV1 LV2 LV3 GND RSTP_N FXO, FXI TSTP_P SXO, SXI VDD MUTE DTMFO Pin # 45 46 47 48 49 50, 51 52 53, 54 55 56 57

HE89C21
HE80000 SERIES
PRTD[7..0]
58 ~ 65
I/O Description B LCD Charge Pump Voltage V1 B LCD Charge Pump Voltage V2 B LCD Charge Pump Voltage V3 P Power ground Input. System Reset input pin. Level trigger, active low on this pin will put the chip in reset I state. External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (`0' O, for RC type and `1' for crystal type). For RC type oscillator, one resistor need to be B connected between FXI and GND. For crystal oscillator, one crystal need to be placed between FXI and FXO. Please refer to application for details. Test input pin. Please bond this pad and reserve a test point on PCB for debugging. I But for improving ESD, please connect this point with zero Ohm resistor to GND. External slow clock pins. Slow clock is clock source for LCD display, TIMER1, O, Time-Base, DTMF generator and other internal blocks. 32768 Hz crystal or resonator I should be used for DTMF generator to function properly. Positive power Input. 0.1 F decoupling capacitors should be placed as close to IC P VDD and GND pads as possible for best decoupling effect. MUTE is open drain type output for muting microphone of telephone speech O network. Dual-Tone Multiple Frequency Tone Output for dialing purpose. It can also be used O as two-channel general purpose tone generator with frequency resolution of 1 Hz. 8-bit bi-directional general purpose I/O port D. The output type of I/O pad can also be selected by mask option MO_DPP[7..0] (`1' for push-pull and `0' for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, `1' must be outputted before reading the pin. B The initial state of PRTD[2..0] can be determined by mask option MO_IH[2..0], while initial state of PRTD[7..3] is always `1'. PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be used as external interrupt sources.
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HE89C21
HE80000 SERIES
4. Pad Diagram
5. Pad Coordinations
Pad No. 1 2 3 4 5 6 7 8 9 10 Pad Name PRTC[5] PRTC[4] PRTC[3] PRTC[2] PRTC[1] PRTC[0] SEG[31] SEG[30] SEG[29] SEG[28] X Coord. Y Coord. -977.5 989.5 -977.5 874.5 -977.5 759.5 -977.5 644.5 -977.5 529.5 -977.5 414.5 -977.5 299.5 -977.5 184.5 -977.5 69.5 -977.5 -45.5 4 Pad No. 35 36 37 38 39 40 41 42 43 44 Pad Name SEG[3] SEG[2] SEG[1] SEG[0] COM[3] COM[2] COM[1] COM[0] LC1 LC2 X Coord. Y Coord. 977.5 -989.5 977.5 -850.5 977.5 -735.5 977.5 -620.5 977.5 -505.5 977.5 -390.5 977.5 -275.5 977.5 -160.5 977.5 -45.5 977.5 69.5 V1.0E
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King Billion Electronics Co., Ltd.
Pad No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Name SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] X Coord. Y Coord. -977.5 -160.5 -977.5 -275.5 -977.5 -390.5 -977.5 -505.5 -977.5 -620.5 -977.5 -735.5 -977.5 -850.5 -977.5 -989.5 -862.5 -989.5 -747.5 -989.5 -632.5 -989.5 -517.5 -989.5 -402.5 -989.5 -287.5 -989.5 -172.5 -989.5 -57.5 -989.5 57.5 -989.5 172.5 -989.5 287.5 -989.5 402.5 -989.5 517.5 -989.5 632.5 -989.5 747.5 -989.5 862.5 -989.5 Pad No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Pad Name LV1 LV2 LV3 GND RSTP_N FXO FXI TSTP_P SXO SXI VDD MUTE DTMFO PRTD[7] PRTD[6] PRTD[5] PRTD[4] PRTD[3] PRTD[2] PRTD[1] PRTD[0] PRTC[7] PRTC[6]
HE89C21
HE80000 SERIES X Coord. Y Coord. 977.5 184.5 977.5 299.5 977.5 414.5 977.7 529.5 977.5 644.5 977.5 759.5 977.5 874.5 977.5 989.5 805 989.5 690 989.5 575 989.5 460 989.5 345 989.5 230 989.5 115 989.5 0 989.5 -115 989.5 -230 989.5 -345 989.5 -460 989.5 -575 989.5 -690 989.5 -805 989.5
6. LCD Power Supply
The LCD power supply is equipped with input power regulator, voltage Tripler, and bias voltage generating resistor network. The input power of MCU is regulated and multiplied by 3 times to generate LV3 to generate the stable driving voltages for LCD driver. The bias voltages for LCD driver are then generated from LV3 using the internally resistor voltage dividing network. With the regulated LCD power, the LCD display can give steady visual effect over a wide range of operating voltage. The built-in regulator must be enabled by mask option MO_ LVRG to function.
LV3 LV2 LV1 LC2 LC1 0.1uF 104
0.1uF
0.1uF
MO_LVRG Function 0 Disable LCD regulator 1 Enable LCD regulator
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HE89C21
HE80000 SERIES
6.1. LCDC Control register
LCD Control Register LCDC controls the functions of LCD driver; such as contrast level, LCD waveform type, On/Off, Blank or not, etc. LCDC Field Field TYPE Value 0 1 BLANK 0 1 LCDE 0 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 TYPE bit 1 bit 0 BLANK LCDE
Function Select Type A LCD waveform Select Type B LCD waveform Normal display LCD display blanked. LCD driver changes only COM output signal, SEG signal remains unchanged. LCD driver disabled, LCD driver has no output signal. LCD driver Enabled
Please note that LCD driver must be turned off before the entering sleep mode. That means user must clear the bit 0 of LCDC to turn off LCD driving circuit before setting bit6 of OP1 to enter sleep mode. Large current might happen if the procedure is not followed. Please also note that LCD driver uses slow clock as clock source. The LCD display will not display normally if it works in Fast clock only mode because the LCD refresh action is too fast.
7. LCD RAM Map
PP=0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 bit7(C3) bit6(C2) bit5(C1) bit4(C0) bit3(C3) bit2(C2) bit1(C1) bit0(C0) F0h S1 S0 F1h S3 S2 F2h S5 S4 F3h S7 S6 F4h S9 S8 F5h S11 S10 F6h S13 S12 F7h S15 S14 F8h S17 S16 F9h S19 S18 FAh S21 S20 FBh S23 S22 FCh S25 S24 FDh S27 S26 FEh S29 S28 FFh S31 S30
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HE89C21
HE80000 SERIES
8. Oscillators
The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to choose from. So that system designer can select oscillator types based on the cost target, timing accuracy requirements etc. With two clock sources available, the system can switch among operation modes of Fast, Slow, Idle, and Sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of application such as power saving, etc. OP1 Field Mode Reset OP2 Field Mode Reset Bit 7 1 R 1 Bit 7 IDLE R/W 0 Bit 6 STOP R/W 0 Bit 6 PNWK R/W Bit 5 SLOW R/W 0 Bit 5 TCWK R/W Bit 4 INTE R/W 0 Bit 4 TBE R/W 0 Bit 3 T2E R/W 0 Bit 3 R/W Bit 2 T1E R/W 0 Bit 1 Z R/W Bit 0 C R/W Bit 0 R/W -
Bit 2 Bit 1 TBS[3..0] R/W R/W -
Crystal, Resonator or RC oscillator can be used as fast clock source. External components should be placed as close to the oscillator pins as possible. The type of oscillator used is selected by mask option MO_FXTAL. MO_FXTAL Fast clock type 0 RC Oscillator. 1 Crystal Oscillator.
VDD FXI R FXI
FXO
C
Slow clock is clock source for LCD display, Timer1, and Timer Base, etc. Crystal oscillator can be used as slow clock. If used in feature phone applications, 32768 Hz crystal is suggested to generate DTMF tone.
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SXI

HE89C21
HE80000 SERIES
33p
32768Hz 33p SXO
If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from slow clock while the other blocks will operate with the fast clock.
9. General Purpose I/O
There are two dedicated general purpose I/O port, PRTC, PRTD. All the I/O Ports are bi-directional and of non- tri-state output structure. The output has weak sourcing (50 A) and stronger sinking (1 mA) capability and each can be configured as push-pull or open-drain output structure individually by mask option. The input port has built-in Schmidt trigger to prevent it from chattering. The hysteresis level of Schmidt trigger is 1/3*VDD. MO_?PP[...] Output Structure 0 Open-drain output 1 Push-pull output When the I/O port is used as input, the weakly high sourcing PMOS can be used as pull-up. Open drain can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a floating pad could cause more power consumption since the noise could interfere with the circuit and cause the input to toggle. A `1' needs to be written to port first before reading the input data from the I/O pin, otherwise, the pin will always be stuck at `0'. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path between pull-up and external circuit. The initial state of most I/O ports is `1' with one exception. The initial state of PRTD[2..0] is determined by mask option MO_IH[2..0]. PRTD Reset Bit7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 MO_IH2 Bit 1 Bit 0 MO_IH1 MO_IH0
MO_IH[2..0] Initial State of PRTD[2..0] 0 0 1 1
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VDD
VDD
HE89C21
HE80000 SERIES
DOUT
Q LATCH Q' MO_?PP
PAD
DIN SCHMIDT Trigger input
10. Timer1
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt will be generated when the counter underflows - counts down to FFFFH. And the counter will be automatically reloaded with the value of T1H and T1L. The clock source of Timer1 is derived from slow clock "SCK" at dual clock or slow clock only mode. And it comes from the fast clock "FCK" at fast clock only mode. Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be set before enabling Timer1.
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HE89C21
HE80000 SERIES
The contents of T1H and T1L almost loaded into Timer1 immediately when Timer1 is turned on after reset.
T1H
T1L
Auto reload when Timer1 underflow
"Timer1 Counter" decreases 1 No
Count TO 0xFFFFh
Start Timer1 Interrupt Request.
Yes
T1_INT
The Timer1 related control registers are list as below: Register Address Field Bit position Mode Description 0x02 TC1_IER 2 R/W 0: TC1 interrupt is disabled. (default) IER 1: TC1 interrupt is enabled. 0x03 T1L[7:0] 7~0 W Low byte of TC1 pre-load value T1L 0x04 T1H[7:0] 7~0 W High byte of TC1 pre-load value T1H 0x09 TC1E 2 R/W 0: TC1 is disabled. (default) OP1 1: TC1 is enabled.
11. Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock "Fsys"/1.5. The system clock "Fsys" varies depending on the operation modes of the MCU. The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded January 20, 2003 10 V1.0E
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with the value of T2H and T2L.
HE89C21
HE80000 SERIES
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value should be set before enabling Timer2.
The contents of T2H and T2L almost loaded into Timer2 immediately when Timer2 is turned on after reset.
T2H
T2L
Auto reload when Timer2 underflow
"Timer2 Counter" decreases 1 No
Count TO 0xFFFFh
Yes Start Timer2 Interrupt Request. T2_INT
The Timer2 related control registers are list as below: Register Address Field Bit position Mode Description 0x02 TC2_IER 1 R/W 0: TC2 interrupt is disabled. (default) IER 1: TC2 interrupt is enabled. 0x05 T2L[7:0] 7~0 W Low byte of TC2 pre-load value T2L 0x06 T2H[7:0] 7~0 W High byte of TC2 pre-load value T2H 0x09 TC2E 3 R/W 0: TC2 is disabled. (default) OP1 1: TC2 is enabled. The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is determined by dividing slow clock with a factor selected in OP2[3..0]. TBE (Time Base Enable) bit January 20, 2003 11 V1.0E
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controls enable or disable of the circuit. OP2 Field Mode Reset Bit 7 IDLE R/W 0 Bit 6 PNWK R/W Bit 5 TCWK R/W Bit 4 TBE R/W 0 Bit 3 R/W Bit 2 Bit 1 TBS[3..0] R/W R/W -
HE89C21
HE80000 SERIES
Bit 0 R/W -
TBE Function 0 Disable Time Base 1 Enable Time Base For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table. TBS[3..0] Interrupt Frequency 0000 16.384 KHz 0001 8.192 KHz 0010 4.096 KHz 0011 2.048 KHz 0100 1.024 KHz 0101 512 Hz 0110 256 Hz 0111 128 Hz 1000 64 Hz 1001 32 Hz 1010 16 Hz 1011 8 Hz 1100 4 Hz 1101 2 Hz 1110 1 Hz 1111 0.5 Hz
12. Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by abnormal hardware activities or program execution. WDT needs to be enabled in Mask Option. MO_WDTE Function 0 WDT disable 1 WDT enable To use WDT function, "CLRWDT" instruction needs to be executed in every possible program path when the program runs normally in order to clears the WDT counter before it overflows, so that the program can operate normally. When abnormal conditions happen to cause the MCU to divert from normal path, the WDT counter will not be cleared and reset signal will be generated.
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WDT is the enabling signal generated by calculating 32768-clock overflow. same as TC1 (Timer1 clock), which uses the same clock count source. clock has stopped.)
HE89C21
HE80000 SERIES Reset Register content is
WDT function can be generated
in Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1
13. Low Voltage Reset
Low voltage reset circuit prevents the CPU from operating below its physical limit. When the supply voltage drops below VDET, the CPU will be held in reset state until the supply voltage rises to VRLS. Then CPU will be released from reset state. VRLS will be higher than VDET by 5% to provide hysteresis and prevent CPU from bouncing back and forth between reset and operating state. MO_LVR_LVL Detection voltage 1.9 volts 00 2.0 volts 01 2.1 volts 10 Release voltage 1.995 volts 2.1 volts 2.205 volts
The low voltage reset circuit can be disabled/enable by mask option MO_LVR_N. MO_LVR_N 0 1 LVR function Enable Disable
The voltage detection circuit is temperature compensated to prevent the detection voltage from drifting with temperature variation.
Vrst
Vdet
Vrls
VDD
14. Dual-Tone Multiple Frequency Generator
The Dual-Tone Multiple Frequency (DTMF) generator is used to generate the Tone Dialing signal used in Telecommunication applications. In fact, it can be used to generate any two channel sine wave signal with frequency ranging from 1 ~ 2047 Hz with 1 Hz resolution. The DTMF generator derives its clock from 32768 Hz oscillator.
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HE89C21
HE80000 SERIES
The DTMF generator is controlled through DTMFC (DTMF Control) Register. It is write only, and can not be to read. The DTMFC register actually maps to Row Register, Column Register and Command Register. So when writing to DTMFC, the actual register being written is determined by Bit 7 and 6. DTMFC ROW HIGH ROW LOW COL HIGH COL LOW COMMAND BIT7 0 0 0 0 1 BIT6 0 0 1 1 1 BIT5 X M5 X M5 HOOK BIT4 M10 M4 M10 M4 BIT3 M9 M3 M9 M3 MUTE BIT2 M8 M2 M8 M2 BIT1 M7 M1 M7 M1 DTMF BIT0 M6 M0 M6 M0 HB(1)/LB( 0)
Bit 5 of command register (HOOK bit) is the main switch of DTMF Generator block. the block will be turned on.
When HOOK Bit
is `1', the entire block will be turned off and all internal registers will be reset. When HOOK Bit is `0',
The Row and Column registers determine the frequencies of two channels sine wave generator. As they are 11-bit register, they need to be divided into high parts and low part when writing. The procedure of changing the Row and Column frequency is by selecting High or Low byte to be written in the command register, write to the target register, then toggle the HB/LB bit, and then write to the second part of the register. When both frequencies are set, the DTMF tone can be sent to DTMFO output by turning on bit 1 (DTMF bit) of command register. When DTMF bit is `1', DTMF signal can be output, and the output is disabled when DTMF bit is `0'. In addition to DTMF generation function, this function block also provides others features which are useful for the phone application. For example, MUTE bit (bit 3) of command register directly controls the state of output pin MUTE. When MUTE bit is `1', the state is MUTE pin is set to high impedance `Z', while MUTE bit is `0', the state of MUTE pin is `0'. This pin is useful for muting the microphone of telephone speech network to prevent speech signal from interfering the DTMF dialing signal when it is been generated.
15. Absolute Maximum Rating
Item Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Sym. Rating Vdd -0.5V ~ 8V Vin -0.5V ~ Vdd+0.5V Vo -0.5V ~ Vdd+0.5V Top 00C ~ 700C Tst -500C ~ 1000C Condition
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HE89C21
HE80000 SERIES
16. Recommended Operating Conditions
Item Supply Voltage Input Voltage Operating Frequency Operating Temperature Storage Temperature Rating 2.4V ~ 5.5V 0.9 Vdd ~ Vdd 0V ~ 0.1Vdd 8MHz Fmax 4MHz Top 00C ~ 700C Tst -500C ~ 1000C Sym. Vdd Vih Vil Condition
Vdd =5.0V Vdd =2.4V
17. AC/DC Characteristics
Test Condition: Temp. = 25, VDD = 3V10%, GND=0V
PARAMETER
Normal mode current Slow mode current Idle mode current Additional current if LCD ON Sleep mode current Input high voltage Input Low Voltage Input Hysteresis Width Output source current Output sink current Input Low Current Input Low Current
Symbol MIN TYP MAX UNIT
IFAST ISLOW IIDLE ILCD ISLEEP VIH VIL VHYS IOH IOL1 IIL2 IIL1 50 1.0 100 20 0.8 0.2 1/3 0.75 6 4 2 1 9 7 3 1 mA A A A
CONDITION
2M ext. R/C 32768 Hz, LCD Disabled 32768 Hz, LCD Disabled LCD Enabled
A VDD Input pins VDD Input pins I/O, RSTP_N, Threshold=2/3VDD(input from low to high) VDD Threshold=1/3VDD(input from high to low) A Output drive high*1, VOH =2.0V mA Output drive low, VOL= 0.4V A I/O, VIL= GND, pull high Internally A RSTP_N, VIL= GND, pull high Internally
1.
The "Output source current" specification is applicable only to the Push-Pull I/O type.
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HE89C21
HE80000 SERIES
18. Application Circuit
VDD 0.1uF 47uF 3.0V + C12 33p MUTE DTMFO PRTD7 PRTD6 PRTD5 PRTD4 PRTD3 PRTD2 PRTD1 PRTD0 PRTC7 PRTC6 Y3 32768Hz 3579545Hz SXO SXI 0 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 C11 33p
PRTC6 PRTC7 PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 DTMFO MUTE VDD SXI SXO
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
22p
VDD
PRTC5 PRTC4 PRTC3 PRTC2 PRTC1 PRTC0 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
PRTC5 PRTC4 PRTC3 PRTC2 PRTC1 PRTC0 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21
HE89C21
TSTP FXI FXO RSTP GND LV3 LV2 LV1 LC2 LC1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2
FXI FXO RESET LV3 LV2 LV1 LC2 LC1 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2
22p
51K
0.1uF 104 0.47uF
0.1uF
0.1uF
19. Important Note
1. Please bond the TSTP_P, RSTP_N and PRTD[7:0] with test points on PCB, which can be soldered and probed, and connect TSTP_P pin with zero ohm resistor to GND (or copper wire which can be cut easily on PCB) for good ESD protection. So that IC testing can be done on PCB, if necessary by removing the 0-ohm resistor and driving TSTP_P pin to high.LV3 must small than 9.0 Volt. Otherwise IC may breakdown.
20. Updated Record
Version Date Section Original Content New Content
January 20, 2003
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20
SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3
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